Digital Validation IP for ASICs and FPGAs

Virtual Display Validation IP Core

The Virtual Display IP is designed to enable automated testing of the output of display controllers with DPI-2 output interface such as the TES CDC "Customizable Display Controller". While visual inspection of display output may be appropriate during the development phase, it is not a viable approach when setting up an automated validation environment. The Virtual Display IP receives the display output signal and writes it to system memory. The content of the system memory can then be accessed via a software API for further evaluation and tests on CPU side.