D/AVE NX – OpenGL ES 2.0 3D graphics IP core for FPGAs and ASICs

D/AVE NX is the latest and most powerful addition to the D/AVE family of rendering cores. It is the first IP to bring 3D graphics OpenGL ES 2.0 rendering (with some ES 3.0 / 3.1 extensions) to the FPGA and SoC world and – with offline-shader compilers – even into MCUs or low-end MPUs with small amounts of memory and bare-metal or RTOS operation systems. Targeted for graphics applications on displays up to 4K x 4K resolution in the Industrial, Medical, Military, Avionics, Automotive and Consumer markets, D/AVE NX is designed to meet the sweet spot of performance and footprint bringing full 3D graphics even down to MCU class devices and into safety critical applications.

By enabling the use of programmable shaders even on small devices, high quality 2D and full 3D applications can be realized using the D/AVE NX core. Support for industry standard APIs like OpenGL ES 2.0 allows for rapid development of high-end user interfaces by leveraging common GUI frameworks like LVGL, Qt or SCADE and makes new, future proof implementations possible.

D/AVE NX can scale easily to fit exactly into the resource / performance sweet spot for a particular application. Entire device families can be equipped with differently scaled variants of the core, making all of them fully software compatible. A single unified software stack and the guarantee to produce exactly the same visual result (at different speeds) allows saving significant development resources.

D/AVE NX is highly efficient as the internal multi-level scheduler can maximize the utilization of every HW element even better than the fixed function pipeline of the successful D/AVE cores could. Scheduling also does not have to be precomputed in the compiler, simplifying the compiler and driver architecture considerably.

Download:
D/AVE NX Product Brief

D/AVE NX Graphics Turnkey System Solution for Intel PSG SoCs


D/AVE NX is provided within evaluation kits for Intel PSG Arria10 and Stratix10 SoCs including a complete solution based on Yocto-Linux and Qt- as well as OpenGL ES 2.0 example applications. The evaluation kits include the D/AVE NX QSys component, drivers and documentation, i.e. everything that is needed for integration, evaluation and prototyping purposes.

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Overview of the components included in the D/AVE NX Turnkey System Solution Evaluation Kit

D/AVE NX Feature & Technology Overview

System Features

  • Scalability throughout the entire design
    • Scaling from tiny footprint up to high end performance with exact same driver / software stack for all versions à same output at different speeds!
  • Unified Shader Architecture
    • Dynamic, fully reconfigurable shaders
    • Efficient support for branches / divergent control flow
    • Fully IEEE compatible floating point ALUs (incl. rounding, denormals etc.)
    • Non-constant varying indexing
    • True integer arithmetic (8bit, 16bit, 32bit)
    • Multi-level caches for shader memory
  • Massively parallel execution with fine grained Multithreading
    • Bandwidth reduction by e.g. on the fly data compression/decompression
    • System security features
      • Stop on bus error for integration with memory protection units
      • Hardware out-of-framebuffer memory access protection

    Rendering

    • Full support of all OpenGL ES 2.0 rendering features (with some OpenGL ES 3.0 / 3.1 extensions)
    • High render quality
      • Highly accurate sub pixel positioning, interpolation and filtering
      • Multiple  anti-aliasing techniques (including MSAA)
    • Effective texture and frame-buffer compression
    • Hardware supported blending (normal alpha, linear colorspace,…)
    • Various texture and framebuffer formats
    • High resolutions: Frame buffers and textures up to 4k x 4k pixels
    • Support for Image Transformation & Warping
    • Composition Engine

    Power Management

    • Memory blocks controlled by Chip Select port
    • Prepared for efficient automatic clock gating
    • Global clock gating as option

    Integration

    • Single clock domain architecture
      • Bus interface clock frequency may differ from core frequency
    • High latency capable
    • Optional internal arbitration to work with a single bus master
    • Adaptors for common bus protocols
      • ARM AMBA: APB for register access, AXI for memory bus master access
      • Intel PSG Avalon as bus adaptors for both register and bus master access
      • Other bus protocols can be easily adapted

    Software Drivers

    TES provides Khronos conform OpenGL ES 2.0 and EGL drivers. The drvers rely on a low level D/AVE NX driver layer abstracting hardware details like the register access and making porting to different CPUs / Operating systems a lot easier.

    All drivers have the following features:

    • Fully reentrant & thread-safe
    • Minimal OS dependency (HAL part separated)
    • No inline assembler required
    • Support for multiple D/AVE NX instances
    • Multi-threading support, i.e. multiple applications can use D/AVE NX concurrently
    • Small memory footprint

    Related Links

    Download:
    D/AVE NX Product Brief