Graphics Processing Units (GPUs) / Vector Graphics Rendering Engines
Hardware IP cores for ASICs and FPGAs and Software IP cores for micro-processors
TES offers a variety of GPU (Graphics Processing Unit) and vectore rendering engine IP cores targeting MCUs, MPUs and FPGAs. Our portfolio covers 2D GPUs, e.g. for ultra-low power devices and state-of-the-art graphical user interfaces (GUIs) in mass-market consumer applications, 2.5D GPUs for more advanced vector graphics applications with 3D graphics elements up to OpenGL ES shader programmable 3D GPUs for premium graphics applications on Ultra-HD displays. With a history of about 20 years our IPs are field proven in automotive and mass market consumer applications.
What makes TES GPUs special and is reflected by our business models is the extremely high level of customizability of our IPs: All our IPs are based on modular, customizable designs and are highly adaptable to meet our customers specific needs concerning functionality, performance, footprint and special system requirements such as functional safety.
Together with our IP cores we provide high-professional engineering support for IP customization, integration, driver-porting and graphics application development.
Hardware Rendering GPU IP Cores
IP cores delivered in VHDL for use in FPGAs, ASICs and SOCs:
D/AVE 2D
Fixed Function 2D GPU / vector graphics rendering engine for MCUs, MPUs and FPGAs
Edge Antialiasing
Max resolution: 2048 x 2048 pixel
Size optimized: <100k gates, < 35kBits memory
Pipeline 1 pixel / cycle
API: D/AVE 2D API
OS Support: Bare Metal / RTOS / Linux
D/AVE HD Family
Fixed Function 2.5D GPU / vector graphics rendering engine with 3D graphics features for MCUs, MPUs and FPGAs
Edge Antialiazing, Multi-Threading Support, Texture & Framebuffer Compression
Max resolution: 4096 x 4096 pixel
Configurable Feature Set: ~230k - 560k ASIC gates, ~67k-120kBits memory
API: D/AVE HD API and optional OpenVG 1.1 API
OS Support: Bare Metal / RTOS / Linux
D/AVE 3D
3D GPU with OpenGL ES 1.1 and OpenVG 1.01 API for MPUs and FPGAs
Edge Based Anti-Aliasing, Texture Compression
Max resolution: 2048 x 2048 pixel
~1200k gates, 200-400kBits memory
Pipeline: 1 pixel / cycle
API: OpenGL ES 1.1 and optional OpenVG 1.01
OS Support: Linux
D/AVE NX
Shader programmable 3D GPU with low footprint OpenGL ES 2.0 API for MCUs, MPUs and FPGAs
Multi-Sample Anti Aliasing (MSAA), Texture & Framebuffer Compression, FP32 ALUs with full 32 bit Integer support
Max resolution: 4096 x 4096 pixel
Configurable Performance (at same feature set): 1 Shader Unti (4 ALUs) up to 4 Shader Units (128 ALUs), ~700k ASIC gates (min)
Pipeline: 2 FP32 FLOPS / ALU / cycle
API: OpenGL ES 2.0 with VULKAN and OpenGL ES 3.x extensions and very low footprint suitable for MCUs, option for offline shader compilation
OS Support: Bare Metal / RTOS / Linux
Outline 2D, 2.5D and 3D GPUs / vector graphics engines for MCUs, MPUs and FPGAs
Software Rendering GPU IP Cores
Highly portable and modular software rendering cores for MPUs and DSPs delivered as library or source code
eGML - embedded Graphics Multiplatform Library
- Highly portable C++ 2D/3D graphics IP core targeting high quality real-time graphics on embedded devices with single 32bit CPU cores like ARM, MIPS, xscale, x86, PowerPC and SH-4.
- RAM ~16KB, ROM150-600KB
eVRU – embedded Vector Rendering Unit
- Feature-rich ANSI-C 2D/3D graphics IP core for small footprint Microcontrollers & CPU+DSP systems with ANSI C API and optional OpenGL ES 1.1 subset API.
- ROM 50-400KB
Related Links
Eval kits and more information: graphics(at)tes-dst(dot)com
Support: dave_support(at)tes-dst(dot)com
Sales: graphics(at)tes-dst(dot)com