Overview

D/AVE 3D is an IP core for 3D graphics applications. This core is available in 2 versions FPGA and for ASIC. This IP has been specifically designed for embedded, automotive and infotainment market with a big emphasis on flexibility both in hardware and the software. Accompanying the core would be an OpenGL-ES 1.1, EGL 1.3 and OpenVG 1.0 1 API.

Download Dave 3D data sheet

• Low resource usage
- Low gate count ( ~1Mio. Gates for ASIC)
- Low internal memory requirements ( ~125 K Memory Bits)
- ~70K Logic elements for FPGAs

• Offers a wide range of graphical primitives
-Lines, Triangles, Quadrangles

• Prepared for easy SoC integration
- ALTERA AVALON support
- ARM AMBA-AHP, ARM AMBA-APB Bus support
- Performance robust to high memory latency
- Single clock domain architecture

• High Performance
- 100 Mio. Pixels/Second fill rate (100 MHz).
- 6,6 Mio. triangles throughput (100 MHz.)
- Early-Z-Test

• High Quality Rendering
- Anti-Aliasing and Sub-Pixel accurate rendering
- Edge-Based-Filtering for image scaling
- Per-Primitive-Anti-Aliasing (settable per edge)
- Static dithering at Framebuffer write back to enhance RGB565 output

• Fully programmable Transform and Lighting Engine
• Extensive Software Stack available
- General Driver
- EGL 1.3 API
- OpenGL ES 1.1 API
- OpenVG 1.01 API

• Textures
- 2048 x 2048 Texture size
- Flexible texture color format handling
- Texture compression
- Texture offset swizzeling

• Framebuffer
- 2048 x 2048 supported
- ARGB8888, ARGB4444, ARGB1555, RGBA5551, RGB565, AL88, AL44, A8
- Blend Modes - Blend, Multiply, Darken, Lighten

Architecture

The system interfaces to D/AVE are very simple in the Altera world it supports all bus interfaces available on Avalon bus architecture. In the SOC world AMBA is supported and additional bus wrappers are easy to implement with the interfaces to D/AVE being very simple Master, Slave and a Interrupt lines. After reset the CPU can configure or can get status information via the SBI (Slave Bus Interface) with data and memory access through the master bus interface.

To deal with unpredictable memory latency, FIFOs are added at all crucial places, which makes D/AVE 3D more performance robust. The pixel pipeline supports early Z-test. D/AVE in a SOC supports multiple pixel pipelines.

Performance

All performance data given are made under the following assumptions:

• 100% cache hit rates
• No latency from external data
• Internal pipeline latency ignored
• 100 MHz.

Fillrate

The Pixel-Pipeline of the D/AVE 3D-IP can produce 1 pixel per cycle, in any configuration.

Vertex Throughput

The vertex throughput depends very much on how many light sources are enabled and if transformation is performed. It also depends on the associated vertex attributes, such as color and texture coordinates.

Triangle Throughput

The triangle throughput depends very much on the number of attributes, which have to be interpolated across the primitive.

Software Interfaces and API

For more information and availability please contact This e-mail address is being protected from spambots. You need JavaScript enabled to view it

Related Links

• Eval Kit : Download eval kit for Cyclone 3C120, Stratix and Arria II GX FPGAs
• User Interface : Guiliani C++ framework & HMI / UI Editor
• Multimedia & Graphics Reference Design : MAGiK
• Support : This e-mail address is being protected from spambots. You need JavaScript enabled to view it
• Sales : This e-mail address is being protected from spambots. You need JavaScript enabled to view it

Update : June 2010

• PCie eval kit for D/AVE 3D now available
• Guiliani eval kit for Renesas SH7723
• D/AVE HD available , eval kit release Q3 2010 3