TES offers a variety of Rendering Hardware IP cores for use in FPGAs, ASICs and SOCs. These cores can by either delivered as QSys component for Intel PSG FPGAs or as RTL code for ASIC developments or integration in other vendors FPGAs.

IP Core Description Footprint
D/AVE 2D 2D graphics rendering engine supporting various blit functions and vector features. <100k gates,
< 35kBits memory

~10k LEs on Intel PSG FPGAs
D/AVE 2D Lite D/AVE 2D configured for minimum footprint on cost of performance but with same feature set. <60k gates,
< 20kBits memory

~6k LEs on Intel PSG FPGAs
D/AVE 3D 3D graphics rendering engine, offers OpenGL ES 1.1 and OpenVG 1.01 API. Offers high performance at 8M tri/sec, Edge-based anti-aliasing. ~1200k gates,
200-400kBits memory

~90k LEs on Intel PSG FPGAs
D/AVE HD Feature-rich 2D/3D graphics rendering engine optimized for highest performance targeting premium graphics on up to 4k x 4k Displays. Full OpenVG 1.1 compliancy. Provides hardware multithreading support and system safety features. 250-500k gates,
80-200kBits memory

~30-50k LEs on Intel PSG FPGAs
3D graphics rendering engine, fully OpenGl ES 2.0/3.x and VULKAN compliant targeting typical embedded graphics and HMI applications on up to 4k x 4k displays. Scalable and with performance/footprint balance to fit on FPGAs and small MPUs. Various configurations (tbd) from 31k LEs up to 100 kLEs and above

Our IP cores are field proven and you might use end products that contain this IP without you even knowing it!
A typical application area is e.g. automotive instrumentation clusters, where the D/AVE cores can be found in a variety of cars.

Update: March 2017


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