TES Physical Implementation Competence Center

What we offer ...

Close collaboration with European clients

  • On-site consulting
  • 6 German design centers with secured design zones
  • One-stop solution for all Digital and Mixed-Signal layout requirements
  • Detailed project management:
    • Customer always knows about the progress of his implementation
    • Milestone deliveries

Established long-term relations with TES' silicon foundry partners

  • Short ramp-up times (new tools and flows) for new projects
  • Physical design experience with technologies from 0.35 um down to 40 nm
  • The right process for your ASIC / ASSP / SoC, choose from
  • TES Physical Implementation Service can also handle processes from other foundries as well as MPW runs for customer's first trial

Some of the markets our implementations are designed for

  • Communication (wired, wireless, GSM, LTE)
  • Digital Consumer
  • Automotive
  • Video processing
  • Signal / Data processing

Balancing performance, cost & yield

  • Appropriate proven EDA design flows - customers' cost/yield & performance requirements are both considered
  • State-of-the-art methods for ambitious projects
    • Multi mode / multi corner optimization with SI- & Xtalk-optimization for improved yield
    • Timing closure and static timing analysis (STA, SSTA)
    • Parallel job processing to handle high complexities
    • Physical implementation of reusable blocks / IP
    • Either flat or hierarchical implementation, depending on customer's and design requirement
  • Supporting best-in-class EDA tools from Cadence, Mentor & Synopsys
  • Experience with high performance / low power implementation, voltage islands, leakage optimization
  • Power analysis and optimization
  • Physical implementation with respect to Design for Manufacturing (DFM) and Design for Yield (DFY)
  • Tape-out in time & within budget

Turnkey-ASIC development capabilities

  • Complementing customers' design activities with the full range of ASIC design services
  • HDL/RTL design from a given specification
  • Netlist Synthesis
  • Place & Route - from RTL to tapeout / GDSII
  • Constraint development & review for CTS and STA - in collaboration with customers' design teams
  • Analog & AMS design services
    • Provided by TES' analog design team
    • Hardmacro / IP development

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Last Modification: 2014/08/01


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